The prior art describes interleaved main stores for writing and fetching data and instructions in order to decrease the access time to the main store by a sub-multiple of the access time for any single module.
The subject invention also uses a plurality of storage modules to derive a decrease in access time for a control store. However, beyond this point, the similarities end between the subject control store and the conventional interleaved main store.
Adddressing for prior main memories, whether interleaved or not, is generated normally from an instruction counter in the system which is operated under control of a macro-program. That addressing technique is not used with the subject invention, and it is replaced by a novel addressing technique.
Prior control stores generally have a relatively large proportion of their capacity dedicated to the next addressing requirement. As a result, a high percentage of the storage capacity of prior control stores is used up by next addressing fields.
Also, the size of the next address field in the conventional control store limits the size of the control store. This limitation is greatly reduced by the subject invention.
U.S. Pat. No. 3,391,394 to Ottaway et al. is the most pertinent known prior art. It describes a non-interleaved and non-overlapped control store comprised of a single ROS module which contains addressable units called storage words. Each storage word contains three microwords which are read out of the ROS as a parallel group. But only one of the three microwords in a readout storage word is selected by a ROS register for subsequent execution. The selected microword has a next address field, which selects the next storage word for ROS readout and one of its three microwords for execution. Thus, during each ROS readout cycle, only one of three readout microwords is available for execution.
In the subject invention only one microword is read out during each cycle, and every microword read from any ROS module is available for execution. Hence, smaller ROS addressable units are available with the subject invention as compared to the prior patent's ROS system with a resulting increase in microword execution speed.
U.S. Pat. No. 3,391,394 also provides USE micro-instructions which use data bits obtained from the data path to modify the address for the next ROS storage word. The subject invention extends the art of USE micro-instructions by teaching their novel implementation in a plural ROS module interleaved and overlapped environment.